The Xilinx XC2C32A-6VQG44C is a 32-macrocell CPLD from the CoolRunner-II family, offering 750 usable gates and 33 I/Os in a compact 44-pin VQFP package measuring 10 x 10 mm. Built on advanced 0.18 µm CMOS technology and operating at a core voltage of 1.8 V, this device delivers a 5.5 ns pin-to-pin delay and a system frequency of up to 200 MHz. The CoolRunner-II family is optimised for low-power operation while maintaining high performance, making it suitable for battery-operated devices and power-sensitive applications.

Low-Power Architecture

The CoolRunner-II CPLD family features a unique low-power design that combines high speed with extremely low standby and dynamic power consumption. The XC2C32A-6VQG44C consumes significantly less power than traditional CPLDs at the same frequency, enabling longer battery life in portable applications. The device includes a power-management feature that automatically disables clocks to unused macrocells, further reducing dynamic power consumption. Zero-power standby mode is also supported, making the device ideal for battery-operated and handheld equipment.

Architecture

The XC2C32A consists of two function blocks interconnected by a low-power Advanced Interconnect Matrix (AIM). Each function block contains 16 macrocells, for a total of 32 macrocells. The AIM provides high connectivity and predictable timing. The 33 I/O pins are distributed across the 44-pin VQFP package. The I/O banks support multiple voltage levels, allowing the device to interface with 3.3V, 2.5V, and 1.8V logic families.

Speed Grade -6

The -6 speed grade indicates a maximum pin-to-pin propagation delay of 5.5 ns, with a system frequency of up to 200 MHz. This makes the XC2C32A one of the fastest CPLDs in its density class. For applications requiring even higher speed, the -5 speed grade (4.6 ns delay) is available within the CoolRunner-II family. The -6 grade provides an optimal balance of speed and power consumption for most applications.

Key Features

• Fastest in-system programming via JTAG (IEEE 1149.1)
• Flexible clocking modes: multiple global clocks and product-term clocks
• Hot-pluggable – can be inserted or removed from a live system without damage
• Advanced design security – prevents unauthorised readback of configuration data
• PLA (Programmable Logic Array) architecture for wide AND-OR logic

Power Considerations

The XC2C32A-6VQG44C is optimised for 1.8 V systems, with an internal supply voltage range of 1.7 V to 1.9 V. The device features industry-leading low power consumption, with standby current measured in microamps. Dynamic power scales linearly with frequency, making the device efficient across a wide range of operating conditions. The combination of 0.18 µm CMOS technology and CoolRunner-II architecture delivers the industry’s best power-performance ratio among CPLDs of its density.

Packaging and Environmental

The XC2C32A-6VQG44C is housed in a 44-pin VQFP (Very Thin Quad Flat Pack) package measuring 10 x 10 mm with a 0.8 mm pitch. The package is RoHS compliant and REACH unaffected. Moisture Sensitivity Level is MSL 3, requiring a floor life of 168 hours after opening. The device is supplied in tray packaging. EAN: 4099879148315.

Development Support

Supported by Xilinx ISE WebPACK and ISE Design Suite (ISE 14.7). Programmable via JTAG using standard cables. The device is not supported by the newer Vivado toolchain. For new designs requiring low power and similar density with modern tool support, consider newer CPLD families or alternative offerings from other manufacturers.

Product Status

The XC2C32A-6VQG44C is marked as obsolete by DigiKey and Octopart, with Mouser indicating “End of Life”. Stock is limited and the device is no longer in active production. For existing designs, verify supply availability before committing to volume production.