Product Specifications
Manufacturer: Xilinx (AMD)
Part Number: XC9572XL-10TQG100C
Product Type: Complex Programmable Logic Device (CPLD)
Series: XC9500XL
Macrocells: 72
Usable Gates: 1,600
Number of I/O: 72
Pin-to-Pin Delay: 10 ns
System Frequency: 100 MHz
Supply Voltage: 3.0 V - 3.6 V
Package: 100-TQFP (14x14 mm)
Operating Temperature: 0°C to 70°C
Product Description
The Xilinx XC9572XL-10TQG100C is a 72-macrocell CPLD from the XC9500XL family, offering 1,600 usable gates and 72 I/Os in a 100-pin TQFP package. Built on 0.35 µm CMOS FastFLASH technology and operating at 3.3 V, it delivers a 10 ns pin-to-pin delay and a system frequency of 100 MHz. This device is the entry point into the XC9500XL family, providing a cost-effective solution for small- to medium-complexity logic integration tasks.
Architecture
The XC9572XL consists of four 54V18 function blocks, each containing 18 macrocells. The FastCONNECT II switch matrix interconnects all function block outputs and input signals. The 72 I/O pins provide ample connectivity for most small- to medium-complexity designs. The I/O pins are 5V tolerant, accepting 5V, 3.3V, and 2.5V signals, with configurable 3.3V or 2.5V output levels. Bus-hold circuitry on all user pin inputs eliminates the need for external pull-up resistors on unused pins.
Speed Grade -10
The -10 speed grade indicates a maximum pin-to-pin propagation delay of 10 ns, with a system frequency of 100 MHz. This provides adequate performance for most glue logic, state machine, and control functions while maintaining reasonable power consumption. For applications requiring higher speed, the -7 speed grade (7.5 ns delay, 178 MHz) is available within the XC9500XL family.
Key Features
- Fast concurrent programming for efficient production programming
- Slew rate control on individual outputs to reduce electromagnetic interference
- Three global clocks and one product-term clock with local clock inversion
- In-system programmable with 10,000 program/erase cycles minimum
- Input hysteresis on all user and boundary-scan pin inputs
Power Considerations
Power dissipation varies with system frequency, design complexity, and output loading. Each macrocell can be individually configured for low-power mode to reduce static power consumption. Unused product terms and macrocells are automatically deactivated by the development software.
Packaging and Environmental
The XC9572XL-10TQG100C is housed in a 100-pin TQFP (Thin Quad Flat Pack) package measuring 14 x 14 mm with a 0.5 mm pitch. The package is RoHS compliant (RoHS3) and REACH unaffected. Moisture Sensitivity Level is MSL 3, requiring a floor life of 168 hours after opening. The device is supplied in tray packaging with 90 pieces per tray. EAN: 4099879145758.
Development Support
Supported by Xilinx ISE WebPACK and ISE Design Suite (ISE 14.7). Programmable via JTAG (IEEE 1149.1) using standard cables. The device is not supported by the newer Vivado toolchain. For new designs requiring similar density and modern tool support, consider the Xilinx CoolRunner-II family.
Product Status
The XC9572XL-10TQG100C is marked as obsolete by DigiKey and “Not recommended for new designs” by TME. Stock is limited and the device is no longer in active production. For existing designs, verify supply availability before committing to volume production.
Resources & Documentation
XC9500XL Starter: 72 Macros, 72 I/Os – Xilinx XC9572XL-10TQG100C
Product Specifications
Manufacturer: Xilinx (AMD)
Part Number: XC9572XL-10TQG100C
Product Type: Complex Programmable Logic Device (CPLD)
Series: XC9500XL
Macrocells: 72
Usable Gates: 1,600
Number of I/O: 72
Pin-to-Pin Delay: 10 ns
System Frequency: 100 MHz
Supply Voltage: 3.0 V - 3.6 V
Package: 100-TQFP (14x14 mm)
Operating Temperature: 0°C to 70°C








