The Xilinx XC9572XL-10VQG64C is a 72-macrocell CPLD from the XC9500XL family, offering 1,600 usable gates and 52 I/Os in a compact 64-pin VQFP package measuring just 10 x 10 mm. Built on 0.35 µm CMOS FastFLASH technology and operating at 3.3 V, it delivers a 10 ns pin-to-pin delay and a system frequency of 100 MHz. This device is designed for applications where board space is at a premium but logic density requirements remain moderate.

Architecture

The XC9572XL consists of four 54V18 function blocks, each containing 18 macrocells. The FastCONNECT II switch matrix interconnects all function block outputs and input signals. The 52 I/O pins are distributed across the 64-pin VQFP package. The I/O pins are 5V tolerant, accepting 5V, 3.3V, and 2.5V signals, with configurable 3.3V or 2.5V output levels. Bus-hold circuitry on all user pin inputs eliminates the need for external pull-up resistors on unused pins.

Speed Grade -10

The -10 speed grade indicates a maximum pin-to-pin propagation delay of 10 ns, with a system frequency of 100 MHz. This provides adequate performance for most glue logic, state machine, and control functions while maintaining reasonable power consumption.

Key Features

• Fast concurrent programming for efficient production programming
• Slew rate control on individual outputs to reduce electromagnetic interference
• Three global clocks and one product-term clock with local clock inversion
• Input hysteresis on all user and boundary-scan pin inputs
• In-system programmable with 10,000 program/erase cycles minimum

Power Considerations

Power dissipation varies with system frequency, design complexity, and output loading. Each macrocell can be individually configured for low-power mode to reduce static power consumption. Unused product terms and macrocells are automatically deactivated by the development software.

Packaging and Environmental

The XC9572XL-10VQG64C is housed in a 64-pin VQFP (Very Thin Quad Flat Pack) package measuring 10 x 10 mm with a 0.5 mm pitch. The package is RoHS compliant (RoHS3) and REACH unaffected. Moisture Sensitivity Level is MSL 3, requiring a floor life of 168 hours after opening. The device is supplied in tray packaging. EAN: 4099879145772.

Development Support

Supported by Xilinx ISE WebPACK and ISE Design Suite (ISE 14.7). Programmable via JTAG (IEEE 1149.1) using standard cables. The device is not supported by the newer Vivado toolchain. For new designs requiring a small-footprint CPLD, consider the Xilinx CoolRunner-II family.

Product Status

The XC9572XL-10VQG64C is marked as “Last Time Buy” by DigiKey. Stock is limited and the device is approaching end of life. For existing designs, verify supply availability and plan for potential migration.