The Xilinx XC2C128-7VQG100C is a 128-macrocell CPLD from the CoolRunner-II family, offering 3,000 usable gates and 80 I/Os in a 100-pin VQFP package measuring 14 x 14 mm. Built on advanced 0.18 µm CMOS technology and operating at a core voltage of 1.8 V, this device delivers a 7 ns pin-to-pin delay and a system frequency of up to 152 MHz. The CoolRunner-II family is optimised for low-power operation while maintaining high performance, making it suitable for communications equipment, industrial control systems, and battery-operated devices.

Low-Power Architecture

The CoolRunner-II CPLD family features a unique low-power design that combines high speed with extremely low standby and dynamic power consumption. The XC2C128-7VQG100C consumes significantly less power than traditional CPLDs at the same frequency, enabling longer battery life in portable applications. The device includes a power-management feature that automatically disables clocks to unused macrocells, further reducing dynamic power consumption. Zero-power standby mode is also supported.

Architecture

The XC2C128 consists of eight function blocks interconnected by a low-power Advanced Interconnect Matrix (AIM). Each function block contains 16 macrocells, for a total of 128 macrocells. The AIM provides high connectivity and predictable timing across all function blocks. The 80 I/O pins are distributed across the 100-pin VQFP package. Two I/O banks are available, each with independently configurable VCCO supplies, supporting 3.3V, 2.5V, and 1.8V signalling.

Speed Grade -7

The -7 speed grade indicates a maximum pin-to-pin propagation delay of 7 ns, with a system frequency of up to 152 MHz. For applications requiring higher speed, the -6 speed grade (6 ns delay) and -5 speed grade (4.6 ns delay) are available within the CoolRunner-II family for the 128-macrocell density. The -7 grade provides an optimal balance of speed and power consumption for most mid-range applications.

Key Features

• Fastest in-system programming via JTAG (IEEE 1149.1)
• Flexible clocking modes: multiple global clocks and product-term clocks
• Hot-pluggable – can be inserted or removed from a live system without damage
• Advanced design security – prevents unauthorised readback of configuration data
• PLA (Programmable Logic Array) architecture with each macrocell capable of up to 40 product terms

Power Considerations

The XC2C128-7VQG100C is optimised for 1.8 V systems, with an internal supply voltage range of 1.7 V to 1.9 V. The device features industry-leading low power consumption, with standby current measured in microamps. Dynamic power scales linearly with frequency, making the device efficient across a wide range of operating conditions. The combination of 0.18 µm CMOS technology and CoolRunner-II architecture delivers the industry’s best power-performance ratio among CPLDs of this density.

Packaging and Environmental

The XC2C128-7VQG100C is housed in a 100-pin VQFP (Very Thin Quad Flat Pack) package measuring 14 x 14 mm with a 0.5 mm pitch. The package is RoHS compliant and REACH unaffected. Moisture Sensitivity Level is MSL 3, requiring a floor life of 168 hours after opening. The device is supplied in tray packaging with 90 pieces per tray. EAN: 4099879148339.

Development Support

Supported by Xilinx ISE WebPACK and ISE Design Suite (ISE 14.7). Programmable via JTAG using standard cables. The device is not supported by the newer Vivado toolchain. For new designs requiring low power and similar density with modern tool support, consider newer CPLD families or alternative offerings from other manufacturers.

Product Status

The XC2C128-7VQG100C is marked as obsolete by DigiKey, with Mouser indicating “End of Life”. RS Online states that the product is being discontinued by the manufacturer. Stock is limited and the device is no longer in active production. For existing designs, verify supply availability before committing to volume production.