Product Specifications
Manufacturer: Xilinx (AMD)
Part Number: XC95144XL-10TQG100I
Product Type: Complex Programmable Logic Device (CPLD)
Series: XC9500XL
Macrocells: 144
Usable Gates: 3,200
Number of I/O: 81
Pin-to-Pin Delay: 10 ns
System Frequency: 100 MHz
Supply Voltage: 3.0 V - 3.6 V
Package: 100-TQFP (14x14 mm)
Operating Temperature: –40°C to 85°C
Product Description
The Xilinx XC95144XL-10TQG100I is a 144-macrocell CPLD from the XC9500XL family, offering 3,200 usable gates and 81 I/Os in a 100-pin TQFP package. Built on 0.35 µm CMOS FastFLASH technology and operating at 3.3 V, it delivers a 10 ns pin-to-pin delay and a system frequency of 100 MHz. The suffix “I” indicates industrial temperature range, making this device suitable for applications where commercial-grade devices (0°C to 70°C) would be inadequate.
Industrial Temperature Grade
Unlike commercial-grade devices that are specified only from 0°C to 70°C, the XC95144XL-10TQG100I is characterised for operation from –40°C to 85°C (ambient temperature). This extended range is critical for applications in outdoor enclosures, unheated industrial environments, automotive systems (non-engine compartment), telecom outdoor cabinets, and any equipment subject to wide temperature swings.
Architecture
The XC95144XL is based on FastFLASH technology, providing in-system programmability with a minimum of 10,000 program/erase cycles. The device consists of eight 54V18 function blocks, each containing 18 macrocells. The 81 I/O pins are distributed across the 100-pin TQFP package. The interconnect matrix between function blocks ensures predictable timing and high logic utilisation. The I/O pins are 5V tolerant, accepting 5V, 3.3V, and 2.5V signals, with configurable 3.3V or 2.5V output levels.
Key Features
- Fast concurrent programming via JTAG
- Slew rate control on individual outputs to reduce EMI
- Three global clocks and one product-term clock with local clock inversion
- Bus-hold circuitry on all user pin inputs
- Individual macrocell low-power mode option
Power Considerations
Power dissipation in the XC9500XL family varies with system frequency, design complexity, and output loading. Each macrocell can be individually configured for low-power mode to reduce static power consumption. Unused product terms and macrocells are automatically deactivated by the development software. In industrial temperature applications where the device may be exposed to high ambient temperatures, proper thermal management should be considered.
Packaging and Environmental
The XC95144XL-10TQG100I is housed in a 100-pin TQFP (Thin Quad Flat Pack) package measuring 14 x 14 mm with a 0.5 mm pitch. The package is RoHS compliant (RoHS3) and REACH compliant. Moisture Sensitivity Level is MSL 3, requiring a floor life of 168 hours after opening. The device is supplied in tray packaging with 90 pieces per tray. EAN: 4099879145727.
Development Support
Supported by Xilinx ISE WebPACK and ISE Design Suite (ISE 14.7). Programmable via JTAG (IEEE 1149.1) using standard cables. The device is not supported by the newer Vivado toolchain. For new designs requiring industrial temperature range and similar density, consider the Xilinx CoolRunner-II family or Artix-7 FPGAs.
Product Status
The XC95144XL-10TQG100I is marked as obsolete by DigiKey. Stock is limited and the device is no longer in active production. For existing designs, verify supply availability before committing to volume production.
Resources & Documentation
Industrial Temperature 144-Macro CPLD – Xilinx XC95144XL-10TQG100I
Product Specifications
Manufacturer: Xilinx (AMD)
Part Number: XC95144XL-10TQG100I
Product Type: Complex Programmable Logic Device (CPLD)
Series: XC9500XL
Macrocells: 144
Usable Gates: 3,200
Number of I/O: 81
Pin-to-Pin Delay: 10 ns
System Frequency: 100 MHz
Supply Voltage: 3.0 V - 3.6 V
Package: 100-TQFP (14x14 mm)
Operating Temperature: –40°C to 85°C
